An integrated wafer scale package using partial wafer bonding and partial wafer dicing techniques has been proposed to integrate a processor and memory chips that are fabricated on different wafers. By using lithography patterning and reactive ion etching, the formation of trenches can be precisely controlled within a tolerance of 100 nanometers to cut out chips from a dummy wafer. An example of this procedure is disclosed in U.S. Pat. No. 6,277,666 to Hays, et al., entitled: “Precisely defined microelectromechanical structures and associated fabrication methods.”
However, the transferring of a chip from a dummy wafer to a target carrier wafer remains a challenge due to uncertainties in the exact size of the chip, the exact size of a pocket on the carrier wafer, and an alignment of the chip within its respective pocket on the carrier wafer.
To accommodate for a potential misalignment during a manufacturing process, a size of the pocket on the carrier wafer should be greater than a size of the chip by at least twice a predetermined process tolerance between the chip and the pocket within the carrier wafer. For example, FIG. 1 illustrates a chip within a pocket fabricated according to a conventional manufacturing process. As shown in FIG. 1, a chip 16 is disposed within a pocket 14. The gap 12 formed between the chip 16 and the pocket 14 is at least twice the size as a process tolerance 18, or “k”. The process tolerance 18 can reach 1 to 2 microns in standard silicon technology. The process tolerance 18 takes into account not only the chip and pocket dimension variations due to mask generation, lithography, substrate etching and dicing, but also accounts for other process variations such as wafer-to-wafer and lot-to-lot variations. Furthermore, to allow the chip to be placed into its corresponding pocket, a small gap is reserved between the sidewalls of the chip and the pocket to accommodate any rough edges and minor debris. Depending on the dicing technique, it is estimated that the total potential misalignment, including process tolerance and reserved gaps on both sides of the chip, can reach 5 microns.
The potential misalignment between the chip and the pocket has an adverse effect on an I/O density of the chip and a first-level global wiring pitch of an integrated wafer scale package. For example, FIG. 2 illustrates adverse effects on an I/O density of a chip and the first-level global wiring pitch of an integrated wafer scale package. As illustrated in FIG. 2, if the misalignment is “s”, the size of the I/O pad 21 is “d”, and the width of global interconnect 23 is also “d”, a landing pad 25 with the size of “d+2s” will be needed to ensure that a proper connection can be made between the I/O pad 21 and the global interconnect 23. Alternatively, the width of the global interconnect 23+ can be increased from “d” to “d+s” to accommodate the potential misalignment and ensure a proper connection between the I/O pad 21′ and the global interconnect 23′. As a result, a minimal pitch of the first-level global interconnect 23′ needs to be increased by “s”.
Therefore, there is a need for a method of manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier wafer.